Company co-CEO Mark Liu said that while the fourth quarter could be a bit rough as customers start their inventory adjustments, TSMC’s sales for the quarter will still outperform those for the third quarter.

Talking to Digitimes Lui said that smartphone demand was affected negatively by macroeconomic factors in the first half of 2016. But apparently smartphone chip clients are ordering again in the second half of the year.

TSMC previously estimated its 2016 revenues would grow 5-10 per cent. The foundry expects to meet the high end of the growth guidance, Liu said. In his speech at the CEO Forum of SEMICON Taiwan 2016. Liu claimed that the foundry industry growth is being driven by the markets for smartphones, HPC, automotive and IoT.

Apps like Pokemon G will require more silicon chips used in mobile devices that will be another growth driver in the future, Liu said.

Courtesy-Fud

According to the slides published by Computerbase.de, both GPUs are based on AMD’s 4th generation Graphics Core Next (GCN 4.0) GPU architecture, offer 2.8 perf/watt improvement compared to the previous generation, have 4K encode and decode capabilities as well as bring DisplayPort 1.3/1.4 and HDR support.

Powering three different graphics cards, these two GPUs will cover different market segments, so the Polaris 10, codename Ellesmere, will be powering both the Radeon RX 480, meant for affordable VR and 1440p gaming as well as the recently unveiled RX 470, meant to cover the 1080p gaming segment. The Polaris 10 packs 36 Compute Units (CUs) so it should end up with 2304 Stream Processors. Both the RX 480 and RX 470 should be coming with 4GB or 8GB of GDDR5 memory, paired up with a 256-bit memory interface. The Ellesmere GPU offers over 5 TFLOPs of compute performance and should peak at 150W.

The Radeon RX 470 should be based on Ellesmere Pro GPU and will probably end up with both lower clocks as well as less Stream Processors and according to our sources close to the company, should launch with a US $179 price tag, while the RX 480 should launch on 29th of June with a US $199 price tag for a reference 4GB version. Most AIB partners will come up with a custom 8GB graphics cards which should probably launch at US $279+.

The Polaris 11 GPU, codename Baffin, will have 16 CUs and should end up with 1024 Stream Processors. The recently unveiled Radeon RX 460 based on this GPU should come with 4GB of GDDR5 memory paired up with a 128-bit memory interface. The Radeon RX 460 targets casual and MOBA gamers and should provide decent competition to the Geforce GTX 950 as both have a TDP of below 75W and do not need additional PCIe power connectors.

According to earlier leaked benchmarks, AMD’s Polaris architecture packs quite a punch considering both its price and TDP so AMD just might have a chance to get a much needed rebound in the market share.

Courtesy-Fud

Digitimes’ deep throats claimed TSMC is expected to achieve certification on its 10nm process in the fourth quarter of 2016, and deliver product samples to the customer for validation in the first quarter of 2017.

This means that TSMC could begin small-volume production for Apple’s A11 chips as early as the second quarter of 2017 and building the chips will likely start to generate revenues at TSMC in the third quarter. The A11-series processor will power the iPhone models slated for launch in the second half of 2017.

TSMC is expected to get two-thirds of the overall A11 chip orders from Apple.

The company is officially refusing to comment on Digitimes’ story, but it does fit into what we have already been told about Jobs’ Mob’s plans for next year.

The 2nd generation High Bandwidth Memory (HBM 2.0) for high-end GPUs might happen in very late Q4 2016 but realistically it probably won’t ship until 2017 in any volume.

The first card that we expect supporting this feature might be the Greenland, a card that AMD might end up calling Vega. Even according Radeon Technology Group’s official GPU roadmap, Vega / Greenland now look like a 2017 product, or at very best, late 2016 card. Nvidia might make the HBM 2.0 version of the Titan card, but we don’t expect to see a Geforce GTX based on Pascal GPU and HBM 2.0 coming to the market this year.

We managed to talk to some of the memory manufactures and they told us that HBM 2.0 is very limited in supply, and limited supply makes things expensive.

It seems that GPUs of 2016, including the new AMD Polaris and the new Geforce, will be stuck with GDDR5 and in best case scenario with GDDR5X from Micron. The word on the street is that both Geforce GTX based on Pascal and AMD/RTG’s Polaris 10 / Ellesmere and Polaris 11 / Baffin might launch at Computex during last days of May or early June 2016.

Courtesy-Fud

For TSMC, Q1 2016 was marked by a reduction of demand for high-end smartphones, while smartphone demand in China and emerging markets had upward momentum. Beginning Q2 2016 and onward, the company expect to get back onto a growth trajectory and is projected to hit a 5 to 10 percent growth rate in 2016.

“Our 10-nanometer technology development is on track,” said company president and co-CEO Mark Liu during the company’s Q4 2015 earnings call. “We are currently in intensive yield learning mode in our technology development. Our 256-megabit SRAM is yielding well. We expect to complete process and product qualification and begin customer product tape-outs this quarter.”

“Our 7-nanometer technology development progress is on schedule as well. TSMC’s 7 nanometer technology development leverage our 10-nanometer development very effectively. At the same time, TSMC’s 7-nanometer offers a substantial density improvement, performance improvement and power reduction from 10-nanometer.

These two technologies, 10-nanometer and 7-nanometer, will cover a very wide range of applications, including application processors for smartphone, high-end networking, advanced graphics, field-programmable gate arrays, game consoles, wearables and other consumer products.”

In Q1 2016, TSMC reached a gross margin of 44.9 percent, an operating margin of 34.6 percent and a net profit margin of 31.8 percent respectively. Going forward into Q2 2016, the company is expecting revenue between ~$6.65 billion and ~$6.74 billion USD, gross margins between 49 and 51 percent, and operating profit margins between 38.5 and 40.5 percent, respectively.

Chips used for communications and industrial uses represented over 80 percent of TSMC’s revenue in FY 2015. The company was also able to improve its margins by increasing 16-nanometer production, and like many other semiconductor companies, is preparing for an expected upswing sometime in 2017.

In February, a 6.4-magnitude earthquake struck southern Taiwan where TSMC’s 12-inch Fab 14 is located, a current site of 16-nanometer production. The company expected to have a manufacturing impact above 1 percent in the region with a slight reduction in wafer shipments for the quarter.

“Although the February 6 earthquake caused some delay in wafer shipments in the first quarter, we saw business upside resulting from demand increases in mid- and low-end smartphone segments and customer inventory restocking,” said Lora Ho, Senior Vice President and Chief Financial Officer of TSMC.

“We expect our business in the second quarter will benefit from continued inventory restocking and recovery of the delayed shipments from the earthquake.”

In fiscal year 2016, the company will spend between $9 and $10 billion on ramping up the 16-nanometer process node, constructing Fab 15 for 12-inch wafers in Nanjing, China, and beginning commercial production of the 10-nanometer FinFET process at this new facility. Samsung and Intel are also expected to start mass production of 10-nanometer products by the end of 2016.

During its Q4 2015 earnings call, company president and co-CEO Mark Liu stated the company is currently preparing and working on a 7-nanometer process node and plans to begin volume production sometime in 2018. Meanwhile, since January 2015, a separate research and development team at TSMC has been laying the groundwork for a 5-nanometer process which the company expects to bring into commercial production sometime in 1H 2020.

So far in Q1 2016, shipments of 16 and 20-nanometer wafers have accounted for around 23 percent of the company’s total wafer revenues.

Courtesy-Fud

The Samsung PM971 built using the company’s Photon controller and runs MLC 3D V-NAND (contrary to the picture above, PC Watch claims it is actually 3-bits per cell). The drive will be available in 128GB, 256GB and 512GB storage capacities and will feature sequential reads up to 1,500MB/s, sequential writes up to 600MB/s, random reads up to 190,000 IOPS and random writes up to 150,000 IOPS.In general, SSDs with BGA packaging are considerably smaller than those using the M.2 form factor, and Intel has claimed that using a PCI-E BGA SSD could allow an increase in battery size by around 10-percent compared to using an M.2 2260 SSD (with GPIO using 1.8v power rail instead of 3.3v), lower thermals than M.2 (from BGA ball conduction to motherboard instead of through M.2 mounting screws), and a vertical height savings of 0.5mm to 1.5mm in notebook devices.

The nice thing about BGA SSDs is that they are “complete” storage solutions and integrate NAND flash memory, the NAND controller and DRAM all into a single package. Currently, there are several BGA M.2 form factors being proposed that will make single-chip SSDs a reality sooner than later as the result of a collaboration between HP, Intel, Lenovo, Micron, SanDisk, Seagate and Toshiba. The four BGA SSD packages proposed are Type 1620, Type 2024, Type 2228 and Type 2828, ranging anywhere between 16 x 20 millimeters and 28 x 28 millimeters with up to 2-millimeter vertical height. It is currently unknown whether the Samsung PM971 adopts any of these proposed BGA M.2 standards.

Based on the demonstration at the 2016 Samsung SSD Forum in Japan, the PM971 offers decent performance thanks to a PCI-E 3.0 x4 interface and the company’s new Photon controller. According to the PC Watch website, the drive is physically smaller than an SD card and Samsung expects device manufacturers and OEMs to begin adoption in the second half of 2016 or the first half of 2017.

Courtesy-Fud

It is starting to look sales teams for the pair are each trying to show that they can use the technology to reduce the most electricity consumption and production costs.

In its yearly result for 2015, TSMC made an announcement that it is planning to enter mass-production system of chips produced by 16-nano FinFET Compact (FFC) process sometime during 1st quarter of this year. TSMC had finished developing 16-nano FFC process at the end of last year. During the announcement TSMC talked up the fact that its 16-nano FFC process focuses on reducing production cost more than before and implementing low electricity.

TSMC is apparently ready for mass-production of 16-nano FFC process sometime during 1st half of this year and secured Huawei’s affiliate called HiSilicon as its first customer.

HiSilicon’s Kirin 950 that is used for Huawei’s premium Smartphone called Mate 8 is produced by TSMC’s 16-nano FF process. Its A9 Chip, which is used for Apple’s iPhone 6S series, is mass-produced using the 16-nano FinFET Plus (FF+) process that was announced in early 2015. By adding FFC process, TSMC now has three 16-nano processors in action.

Samsung is not far behind it has mass-produced Gen.2 14-nano FinFET using a process called LPP (Low Power Plus). This has 15 per cent lower electricity consumption compared to Gen.1 14-nano process called LPE (Low Power Early).

Samsung Electronics’ 14-nano LPP process was seen in the Exynos 8 OCTA series that is used for Galaxy S7 and Qualcomm’s Snapdragon 820. But Samsung Electronics is also preparing for Gen.3 14-nano FinFET process.

Vice-President Bae Young-chang of Samsung’s LSI Business Department’s Strategy Marketing Team said it will use a process similar to the Gen.2 14-nano process.

Both Samsung and TSMC might have a few problems. It is not clear what the yields of these processes are and this might increase the production costs.

Even if Samsung Electronics and TSMC finish developing 10-nano process at the end of this year and enter mass-production system next year, but they will also have to upgrade their current 14 and 16-nano processes to make them more economic.

Even if 10-nano process is commercialized, there still will be many fabless businesses that will use 14 and 16-nano processes because they are cheaper. While we might see a few flagship phones using the higher priced chips, it might be that we will not see 10nm in the majority of phones for years.

Courtesy-Fud

Samsung’s new HBM solution will be used in high-performance computing (HPC), advanced graphics, network systems and enterprise servers, and is said to offer DRAM performance that is “seven times faster than the current DRAM performance limit”.

This will apparently allow faster responsiveness for high-end computing tasks including parallel computing, graphics rendering and machine learning.

“By mass producing next-generation HBM2 DRAM, we can contribute much more to the rapid adoption of next-generation HPC systems by global IT companies,” said Samsung Electronics’ SVP of memory marketing, Sewon Chun.

“Also, in using our 3D memory technology here, we can more proactively cope with the multifaceted needs of global IT, while at the same time strengthening the foundation for future growth of the DRAM market.”

The 4GB HBM2 DRAM, which uses Samsung’s 20nm process technology and advanced HBM chip design, is specifically aimed at next-generation HPC systems and graphics cards.

“The 4GB HBM2 package is created by stacking a buffer die at the bottom and four 8Gb core dies on top. These are then vertically interconnected by TSV holes and microbumps,” explained Samsung.

“A single 8Gb HBM2 die contains over 5,000 TSV holes, which is more than 36 times that of an 8Gb TSV DDR4 die, offering a dramatic improvement in data transmission performance compared to typical wire-bonding based packages.”

Samsung’s new DRAM package features 256GBps of bandwidth, which is double that of an HBM1 DRAM package. This is equivalent to a more than seven-fold increase over the 36GBps bandwidth of a 4Gb GDDR5 DRAM chip, which has the fastest data speed per pin (9Gbps) among currently manufactured DRAM chips.

The firm’s 4GB HBM2 also enables enhanced power efficiency by doubling the bandwidth per watt over a 4Gb GDDR5-based solution, and embeds error-correcting code functionality to offer high reliability.

Samsung plans to produce an 8GB HBM2 DRAM package this year, and by integrating this into graphics cards the firm believes designers will be able to save more than 95 percent of space compared with using GDDR5 DRAM. This, Samsung said, will “offer more optimal solutions for compact devices that require high-level graphics computing capabilities”.

Samsung will increase production volume of its HBM2 DRAM over the course of the year to meet anticipated growth in market demand for network systems and servers. The firm will also expand its line-up of HBM2 DRAM solutions in a bid to “stay ahead in the high-performance computing market”.

Courtesy-TheInq

Based on the firm’s fourth generation Graphics Core Next (GCN) architecture and built using a 14nm FinFET fabrication process, the upcoming architecture is a big jump from the current 28nm process.

AMD said that it expects shipments of Polaris GPUs to begin in mid-2016, offering improvements such as HDR monitor support and better performance-per-watt.

The much smaller 14nm FinFET process means that Polaris will deliver “a remarkable generational jump in power efficiency”, according to AMD, offering fluid frame rates in graphics, gaming, virtual reality and multimedia applications running on small form-factor thin and light computer designs.

“Our new Polaris architecture showcases significant advances in performance, power efficiency and features,” said AMD president and CEO Lisa Su. “2016 will be a very exciting year for Radeon fans driven by our Polaris architecture, Radeon Software Crimson Edition and a host of other innovations in the pipeline from our Radeon Technologies Group.”

The Polaris architecture features AMD’s fourth-generation GCN architecture, a next-generation display engine with support for HDMI 2.0a and DisplayPort 1.3, and next-generation multimedia features including 4K h.265 encoding and decoding.

GCN enables gamers to experience high-performance video games with Mantle, a tool for alleviating CPU bottlenecks such as API overhead and inefficient multi-threading. Mantle, which is basically AMD’s answer to Microsoft’s Direct X, enables improvements in graphics processing performance. In the past, AMD has claimed that Kaveri teamed with Mantle to enable it to offer built-in Radeon dual graphics to provide performance boosts ranging from 49 percent to 108 percent.

The new GPUs are being sampled to OEMs at the moment and we can expect them to appear in products by mid-2016, AMD said. Once they are in the market, we can expect to see much thinner form factors in devices thanks to the much smaller 14nm chip process.

Courtesy-TheInq

Apparently the fruity cargo cult Apple has already signed up to adopt the technology, which means that the rest of the world’s press will probably notice.

According to the Commercial Times TSMC will have 85,000-100,000 wafers fabricated with the foundry’s in-house developed InFo packaging technology in the second quarter of 2016.

TSMC has disclosed its InFO packaging technology will be ready for mass production in 2016. Company president and co-CEO CC Wei remarked at an October 15 investors meeting that TSMC has completed construction of a new facility in Longtan, northern Taiwan.

TSMC’s InFo technology will be ready for volume production in the second quarter of 2016, according to Wei.

TSMC president and co-CEO Mark Liu disclosed the company is working on the second generation of its InFO technology for several projects on 10nm and 7nm process nodes.

Source-http://www.thegurureview.net/computing-category/tsmc-goes-fan-out-wafers.html