The new Mali GPU can push enough pixels on the local display it is more likely that it is interested in using the technology for streaming.

Many smartphones can record 4K video and this means that smartphones could be a home to high resolution content which can be streamed to a large, high resolution screen.

It looks like Mali DP650can juggle the device’s native resolution and the external display’s own resolution and the variable refresh rates. At least that is what ARM says it can do.

The GPU is naturally able to handle different resolutions but it is optimized for a “2.5K”, which means WQXGA (2560×1600) on tablets and WQHD (2560×1440) on smartphones, but also Full HD (1920×1080) for slightly lower end devices.

Mark Dickinson, general manager, media processing group, ARM said: “The Mali-DP650 display processor will enable mobile screens with multiple composition layers, for graphics and video, at Full HD (1920×1080 pixels) resolutions and beyond while maintaining excellent picture quality and extending battery life,”

“Smartphones and tablets are increasingly becoming content passports, allowing people to securely download content once and carry it to view on whichever screen is most suitable. The ability to stream the best quality content from a mobile device to any screen is an important capability ARM Mali display technology delivers.”

ARM did not say when the Mali-DP650 will be in the shops or which chips will be the first to incorporate its split-display mode feature.

Courtesy-Fud

It is starting to look sales teams for the pair are each trying to show that they can use the technology to reduce the most electricity consumption and production costs.

In its yearly result for 2015, TSMC made an announcement that it is planning to enter mass-production system of chips produced by 16-nano FinFET Compact (FFC) process sometime during 1st quarter of this year. TSMC had finished developing 16-nano FFC process at the end of last year. During the announcement TSMC talked up the fact that its 16-nano FFC process focuses on reducing production cost more than before and implementing low electricity.

TSMC is apparently ready for mass-production of 16-nano FFC process sometime during 1st half of this year and secured Huawei’s affiliate called HiSilicon as its first customer.

HiSilicon’s Kirin 950 that is used for Huawei’s premium Smartphone called Mate 8 is produced by TSMC’s 16-nano FF process. Its A9 Chip, which is used for Apple’s iPhone 6S series, is mass-produced using the 16-nano FinFET Plus (FF+) process that was announced in early 2015. By adding FFC process, TSMC now has three 16-nano processors in action.

Samsung is not far behind it has mass-produced Gen.2 14-nano FinFET using a process called LPP (Low Power Plus). This has 15 per cent lower electricity consumption compared to Gen.1 14-nano process called LPE (Low Power Early).

Samsung Electronics’ 14-nano LPP process was seen in the Exynos 8 OCTA series that is used for Galaxy S7 and Qualcomm’s Snapdragon 820. But Samsung Electronics is also preparing for Gen.3 14-nano FinFET process.

Vice-President Bae Young-chang of Samsung’s LSI Business Department’s Strategy Marketing Team said it will use a process similar to the Gen.2 14-nano process.

Both Samsung and TSMC might have a few problems. It is not clear what the yields of these processes are and this might increase the production costs.

Even if Samsung Electronics and TSMC finish developing 10-nano process at the end of this year and enter mass-production system next year, but they will also have to upgrade their current 14 and 16-nano processes to make them more economic.

Even if 10-nano process is commercialized, there still will be many fabless businesses that will use 14 and 16-nano processes because they are cheaper. While we might see a few flagship phones using the higher priced chips, it might be that we will not see 10nm in the majority of phones for years.

Courtesy-Fud

According to Ars Technica Under the handle “GPUOpen” AMD is releasing a slew of open-source software and tools to give developers of games, heterogeneous applications, and HPC applications deeper access to the GPU and GPU resources.

In a statement AMD said that as a continuation of the strategy it started with Mantle, it is giving even more control of the GPU to developers.

“ As console developers have benefited from low-level access to the GPU, AMD wants to continue to bring this level of access to the PC space.”

The AMD GPUOpen initiative is meant to give developers the ability to use assets they’ve already made for console development. They will have direct access to GPU hardware, as well as access to a large collection of open source effects, tools, libraries and SDKs, which are being made available on GitHub under an MIT open-source license.

AMD wants GPUOpen will enable console-style development for PC games through this open source software initiative. It also includes an end-to-end open source compute infrastructure for cluster-based computing and a new Linux software and driver strategy

All this ties in with AMD’s Boltzmann Initiative and an HSA (Heterogeneous System Architecture) software suite that includes an HCC compiler for C++ development. This was supposed to open the field of programmers who can use HSA. A new HCC C++ compiler was set up to enable developers to more easily use discrete GPU hardware in heterogeneous systems.

It also allows developers to convert CUDA code to portable C++. According to AMD, internal testing shows that in many cases 90 percent or more of CUDA code can be automatically converted into C++ with the final 10 percent converted manually in the widely popular C++ language. An early access program for the “Boltzmann Initiative” tools is planned for Q1 2016.

AMD GPUOpen includes a new Linux driver model and runtime targeted at HPC Cluster-Class Computing. The headless Linux driver is supposed to handle high-performance computing needs with low latency compute dispatch and PCI Express data transfers, peer-to-peer GPU support, Remote Direct Memory Access (RDMA) from InfiniBand that interconnects directly to GPU memory and Large Single Memory Allocation support.

Apparently the fruity cargo cult Apple has already signed up to adopt the technology, which means that the rest of the world’s press will probably notice.

According to the Commercial Times TSMC will have 85,000-100,000 wafers fabricated with the foundry’s in-house developed InFo packaging technology in the second quarter of 2016.

TSMC has disclosed its InFO packaging technology will be ready for mass production in 2016. Company president and co-CEO CC Wei remarked at an October 15 investors meeting that TSMC has completed construction of a new facility in Longtan, northern Taiwan.

TSMC’s InFo technology will be ready for volume production in the second quarter of 2016, according to Wei.

TSMC president and co-CEO Mark Liu disclosed the company is working on the second generation of its InFO technology for several projects on 10nm and 7nm process nodes.

Source-http://www.thegurureview.net/computing-category/tsmc-goes-fan-out-wafers.html

VR-World says that stage one results are finished and where shown off this week at SC15. This included a Heterogeneous Compute Compiler (HCC); a headless Linux driver and HSA runtime infrastructure for cluster-class, High Performance Computing (HPC); and the Heterogeneous-compute Interface for Portability (HIP) tool for porting CUDA-based applications to C++ programming.

AMD hopes the tools will drive application performance from machine learning to molecular dynamics, and from oil and gas to visual effects and computer-generated imaging.

Jim Belak, co-lead of the US Department of Energy’s Exascale Co-design Center in Extreme Materials and senior computational materials scientist at Lawrence Livermore National Laboratory said that AMD’s Heterogeneous-compute Interface for Portability enables performance portability for the HPC community.

“The ability to take code that was written for one architecture and transfer it to another architecture without a negative impact on performance is extremely powerful. The work AMD is doing to produce a high-performance compiler that sits below high-level programming models enables researchers to concentrate on solving problems and publishing groundbreaking research rather than worrying about hardware-specific optimizations.”

The new AMD Boltzmann Initiative suite includes an HCC compiler for C++ development, greatly expanding the field of programmers who can leverage HSA.

The new HCC C++ compiler is a key tool in enabling developers to easily and efficiently apply the hardware resources in heterogeneous systems. The compiler offers more simplified development via single source execution, with both the CPU and GPU code in the same file.

The compiler automates the placement code that executes on both processing elements for maximum execution efficiency.

Source- http://www.thegurureview.net/computing-category/amd-appears-to-be-pushing-its-boltzmann-plan.html

Over the last few months both have been busy with new releases. Nvidia has its GeForce GTX 950 and GTX 980 Ti, while AMD put its first HBM-powered cards in the Radeon R9 Fury X, Fury and the super-small R9 Nano into the shops.

According to JPR, overall GPU shipments are up quarter-over-quarter – with AMD’s overall GPU shipments up 15.8 per cent. But before AMD fanboys get all excited by a surprise return to form from AMD, JPR said that that NVIDIA “had an exceptionally strong quarter”. Nvidia saw an uptick of 21.3 per cent.

The PC market as a whole increased by 7.5 per cent quarter-over-quarter but decreased 9 per cent year-over-year. Nivida’s discrete GPU shipments were up 26.3 per cent according to JPR, while AMD’s discrete GPUs spiked by 33 per cent.

AMD’s mobile GPU shipments for notebooks increased by 17 per cent, while NVIDIA had 14 per cent.

Designed for demanding embedded needs, the processors incorporate the newest AMD 64-bit x86 CPU core (“Excavator”), plus third-generation Graphics Core Next GPU architecture, and better power management for reduced energy consumption.

AMD tells us that combined, these chips provide industry-leading graphics performance and key embedded features for next-generation designs. The SOC architecture enables simplified, small form factor board and system designs from AMD customers and a number of third party development platform providers.

What AMD brings to the party is its graphics and multimedia performance, including capability for hardware-accelerated decode of 4K video playback and support for the latest DDR4 memory.
Jim McGregor, principal analyst, TIRIAS Research said that AMDs push into x86 embedded platforms is paying off with an increasing number of customers and applications.

“There is a need for immersive graphics, high-quality visualization, and parallel computing in an increasing number of embedded applications. Across these fronts, the AMD Embedded R-Series SOC is a very compelling solution.”

Scott Aylor, corporate vice president and general manager, AMD Embedded Solutions said that his outfit’s AMD Embedded R-Series SOC is a strong match for these needs in a variety of industries including digital signage, retail signage, medical imaging, electronic gaming machines, media storage, and communications and networking.

“The platform offers a strong value proposition for this next generation of high-performance, low-power embedded designs.”

The new AMD Embedded R-Series SOCs offer 22 percent improved GPU performance when compared to the 2nd Generation AMD Embedded R-Series APU2 and a 58 percent advantage against the Intel Broadwell Core i7 when running graphics-intensive benchmarks.

AMD released some of the specs for its integrated AMD Radeon graphics including:

Up to eight compute units4 and two rendering blocks

GPU clock speeds up to 800MHz resulting in 819 GFLOPS

•DirectX 12 support

Fully HSA Enabled

The AMD Embedded R-Series SOC was architected with embedded customers in mind and includes features such as industrial temperature support, dual-channel DDR3 or DDR4 support with ECC (Error Correction Code), Secure Boot, and a broad range of processor options.

It has a configurable thermal design power (cTDP) allows designers to adjust the TDPs from 12W to 35W in 1W increments for greater flexibility.

The SOC also has a 35 percent reduced footprint when compared to the 2nd Generation AMD Embedded R-Series APU, making it an excellent choice for small form factor applications.

AMD said that the range is the first embedded processor with dual-channel 64-bit DDR4 or DDR3 with Error-Correction Code (ECC), with speeds up to DDR4-2400 and DDR3-2133, and support for 1.2V DDR4 and 1.5V/1.35V DDR3.

Its dedicated AMD Secure Processor supports secure boot with AMD Hardware Validated Boot (HVB) and initiates trusted boot environment before starting x86 cores
It has a high-performance Integrated FCH featuring PCIe Gen3 USB3.0, SATA3, SD, GPIO, SPI, I2S, I2C, and UART

The AMD Embedded R-Series SOC provides industry-leading ten-year longevity of supply. The processors support Microsoft Windows 7, Windows Embedded 7 and 8 Standard, Windows 8.1, Windows 10, and AMD’s all-open Linux driver including Mentor Embedded Linux from Mentor Graphics and their Sourcery CodeBench IDE development tools.

It will be interesting to see if AMD can make up the ground it has lost on PCs and higher ticket items. Most of the company still appears to be in a holding pattern until Zen arrives.

Courtesy-http://www.thegurureview.net/computing-category/will-amds-newest-soc-save-the-company.html

The new Mali-470 GPU has half the power consumption and two times the energy efficiency of the Mali-400, and is designed for next-generation wearables and IoT devices such as industrial control panels and healthcare monitors that rely on low-cost and low-power chips.

The Mali-470 supports OpenGL ES 2.0, used by Android and Android Wear, hinting that the GPU could also find its way into low-cost smartphones. If not, ARM promises that the chip will bring smartphone-quality visuals to wearable and IoT devices, supporting screen resolutions of up to 640×640 on single-core devices, and higher resolutions for multi-core configurations.

ARM envisions the new GPU paired with its efficient Cortex-A7 or A53 CPU designs for a low-power SoC.

“ARM scrutinises every milliwatt across the entire SoC to enable OEMs to optimize energy efficiency and open up new opportunities,” said Mark Dickinson, vice president and general manager of ARM’s multimedia processing group.

“Tuning efficiency is particularly relevant for devices requiring sophisticated graphics on a low power budget such as wearables, entry-level smartphones and IoT devices. The Mali-470 has been designed to meet this demand by enabling a highly capable user interface while being extremely energy efficient.”

ARM expects the first SoCs using the GPU be ready by the end of 2016, meaning that the chip will start showing up in devices the following year.

The launch of the Mali-470 GPU comes just hours after ARM announced plans to pick up the product portfolio and other business assets of Carbon Design Systems, a supplier of cycle-accurate virtual prototyping solutions.

The deal will see Carbon’s staff transfer to ARM, where the chip firm will make use of the Massachusetts-based outfit’s expertise in virtual prototypes. This will enable ARM to iron out any bugs and make improvements to chips before they move to foundries for production.

ARM also said that Carbon will help the firm enhance its capability in SoC architectural exploration, system analysis and software bring-up.

Courtesy-TheInq

The outfit has been going through hell lately. Last month AMD ace CPU architect Jim Keller stepped away from the company after completing his work on Zen.

Rogers was one of AMD’s high-ranking technology and engineering corporate fellows, and been responsible for helping to develop the software ecosystem behind AMD’s heterogeneous computing products and the Heterogeneous System Architecture.

He was a public figure for AMD and active on the software development and evangelism side, frequently presenting the latest HSA tech and announcements for AMD at keynotes and conferences.

While he is not the only person working on the software side of HSA at AMD, Rogers’ role in its development is important. Rogers was a major contributor to the HSA Foundation, helping to initially found it in 2012. He served as the Foundation’s president until he left AMD.

It seems his defection was kept secret, and took place sometime this quarter and did not manage to leak.

According to his LinkedIn profile Phil Rogers is now Nvidia’s “Chief Software Architect – Compute Server” which is similar to what he was doing over at AMD. Nvidia is not a member of the HSA Foundation, but they are currently gearing up for the launch of the Pascal GPU family, which has some features that overlap well with Phil Rogers’ expertise.

Pascal’s NVLink CPU & GPU interconnect would allow tightly coupled heterogonous computing similar to what AMD has been working on. It makes a fair bit of sense for Nvidia to bring over a heterogeneous compute specialist makes a great deal of sense.

Rogers’ departure from AMD will have to be mentioned on the earnings call on the 15th. AMD’s Gregory Stoner will probably replace him. Stoner is AMD’s current Senior Director of Compute Solutions Technology and long-time Vice President of the HSA Foundation.

Source-http://www.thegurureview.net/computing-category/is-amd-losing-top-scientist-to-nvidia.html

According to EETimes Paul Boudre, who claimed that SOI is already being used by Apple and Intel even though neither company is broadcasting it. SOI appears to be on track to major market penetration even while the rest of the industry is talking FinFETs.

GlobalFoundries general manager Rutger Wijburg told the SEMICON Europa 2015 that his outfit’s 22-nanometer “22FDX” SOI platform delivers FinFET-like performance but at a much lower power point and at a cost comparable to 28-nanometer planar technologies.

The 300-millimeter $250 million FD-SOI foundry here in the “Silicon Saxony” area of Germany, builds on 20 years of GlobalFoundries’ investments in Europe’s largest semiconductor fabs.

GlobalFoundries said it will extend Moore’s Law by using fully-deleted silicon-on-insulator (FD-SOI) transistors on wafers bought from Soitec.

Many had thought that if GloFlo’s FD-SOI gamble paid off then it would be a while before FinFET would have a serious rival. But Boudre’s claims suggests that SOI is already being used.

Customers like Intel and OEMs supplying fully-deleted silicon-on-insulator (FD-SOI) RF transistors to Apple proves that SOI and Soitec are past the cusp of the growth curve, destined to ramp up exponentially.

The problem for Soitec is no one is really talking about it. Chipzilla is committed to the FinFET, because it is higher performance than FD-SOI, even though it is higher power too.
Boudre said that it was supplying SOI wafers to Intel for other applications that don’t require high-performance. For instance, our wafers are very good for their silicon photonics projects.

Apple is already using SOI for several radio frequency (RF) chips in their front-ends, because they use 20-times less power. The iPhone is still using gallium arsenide (GaAs) for its power amplifier (PA) because it needs the high-power device for good connections, but for other RF front-end chips, and in fact for all the chips that they want to keep “always on,” the lower power consumption of FD-SOI is pushing the smartphone makers to Soitec, Boudre said.

SOI wafers cost three-times as much as bulk silicon but the cost per die is less because of the simplified processing steps including fewer masks.

Normally GPS chips run on 0.8 volts and consume over 20 milliamps, so they must be turned off most of the time. But when they are made with SOI wafers, they can run on 0.4 volts and consume only 1 milliamp. The mobile device to leave them on all the time and new and more accurate location sensing and new kinds of location-based applications can be developed.

What is amusing then is that Intel’s reason for going with FinFETs was that SOI wafers were too expensive but it did find a use for it.

GlobalFoundries’ Saxony fab will offer four varieties of its 22FDX process.

FDX-ulp for the mainstream and low-cost smartphone market. This will use body-biasing to beat FinFETs on power, but equal them in performance.

FDX-uhp for networking applications using analogue integration to match FinFETs while minimizing energy consumption

FDX-ull for ultra-low power required by wearables and Internet of Things applications. This will have a 1 picoamp per micron leakage

DDX-rfa for radio frequency (RF) analogue applications delivering 50 percent lower power and reduced system costs for LTE-A cellular transceivers, high-order multiple-input/multiple-output (MIMO) WiFi combo chips and millimeter wave radar.

Courtesy-http://www.thegurureview.net/computing-category/ibm-and-intel-going-goflo-soi.html