More Details Uncovered On AMD’s ZEN Cores

Our well informed industry sources have shared a few more details about the AMD’s 2016 Zen cores and now it appears that the architecture won’t use the shared FPU like Bulldozer.

The new Zen uses a SMT Hyperthreading just like Intel. They can process two threads at once with a Hyperthreaded core. AMD has told a special few that they are dropping the “core pair” approach that was a foundation of Bulldozer. This means that there will not be a shared FPU anymore.

Zen will use a scheduling model that is similar to Intel’s and it will use competitive hardware and simulation to define any needed scheduling or NUMA changes.

Two cores will still share the L3 cache but not the FPU. This because in 14nm there is enough space for the FPU inside of the Zen core and this approach might be faster.

We mentioned this in late April where we released a few details about the 16 core, 32 thread Zen based processor with Greenland based graphics stream processor.

Zen will apparently be ISA compatible with Haswell/Broadwell style of compute and the existing software will be compatible without requiring any programming changes.

Zen also focuses on a various compiler optimisation including GCC with target of SPECint v6 based score at common compiler settings and Microsoft Visual studio with target of parity of supported ISA features with Intel.

Benchmarking and performance compiler LLVM targets SPECint v6 rate score at performance compiler settings.

We cannot predict any instruction per clock (IPC improvement) over Intel Skylake, but it helps that Intel replaced Skylake with another 14nm processor in later part of 2016. If Zen makes to the market in 2016 AMD might have a fighting chance to narrow the performance gap between Intel greatest offerings.

Courtesy-Fud

AMD Coherent Data Reaches 100 GBs

After a lot of asking around, we can give you some actual numbers about the AMD’s coherent fabric.

The inter-connecting technology already sounded very promising, but now we have the actual number. The HSA, Heterogeneous System Architecture MCM (Multi Chip Module) that AMD is working on can give you almost seven times faster score than the traditional PCIe interface.

Our industry sources have confirmed that with 4 GMI (Global Memory Interconnect) links AMD’s CPU and GPU can talk at 100GB/s. the traditional PCIe 16X provides 15GB/s at about 500 ns latency. Data Fabric eliminates PCIe latency too.

AMD will be using this technology with the next gen Multi Chip module that packs a Zeppelin CPU (most likely packed with a bunch of ZEN cores) and a Greenland GPU that of course comes with super fast HBM (High Bandwidth Memory). The Greenland and HBM can communicate at 500 GB/s and can provide highest performance GPU with 4+ teraflops.

This new MCM package based chip will also talk with DDR4 3200 memory at 100GB/s speed making it quite attractive for the HSA computation oriented customers.

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Will Arm/Atom CPUs Replace Xeon/Opteron?

Analyst are saying that smartphone chips could one day replace the Xeon and Opteron processors used in most of the world’s top supercomputers. In a paper in a paper titled “Are mobile processors ready for HPC?” researchers at the Barcelona Supercomputing Center wrote that less expensive chips bumping out faster but higher-priced processors in high-performance systems.

In 1993, the list of the world’s fastest supercomputers, known as the Top500, was dominated by systems based on vector processors. They were nudged out by less expensive RISC processors. RISC chips were eventually replaced by cheaper commodity processors like Intel’s Xeon and AMD Opteron and now mobile chips are likely to take over.

The transitions had a common thread, the researchers wrote: Microprocessors killed the vector supercomputers because they were “significantly cheaper and greener,” the report said. At the moment low-power chips based on designs ARM fit the bill, but Intel is likely to catch up so it is not likely to mean the death of x86.

The report compared Samsung’s 1.7GHz dual-core Exynos 5250, Nvidia’s 1.3GHz quad-core Tegra 3 and Intel’s 2.4GHz quad-core Core i7-2760QM – which is a desktop chip, rather than a server chip. The researchers said they found that ARM processors were more power-efficient on single-core performance than the Intel processor, and that ARM chips can scale effectively in HPC environments. On a multi-core basis, the ARM chips were as efficient as Intel x86 chips at the same clock frequency, but Intel was more efficient at the highest performance level, the researchers said.

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Do Supercomputers Lead To Downtime?

As supercomputers grow more powerful, they’ll also become more susceptible to failure, thanks to the increased amount of built-in componentry. A few researchers at the recent SC12 conference, held last week in Salt Lake City, offered possible solutions to this growing problem.

Today’s high-performance computing (HPC) systems can have 100,000 nodes or more — with each node built from multiple components of memory, processors, buses and other circuitry. Statistically speaking, all these components will fail at some point, and they halt operations when they do so, said David Fiala, a Ph.D student at the North Carolina State University, during a talk at SC12.

The problem is not a new one, of course. When Lawrence Livermore National Laboratory’s 600-node ASCI (Accelerated Strategic Computing Initiative) White supercomputer went online in 2001, it had a mean time between failures (MTBF) of only five hours, thanks in part to component failures. Later tuning efforts had improved ASCI White’s MTBF to 55 hours, Fiala said.

But as the number of supercomputer nodes grows, so will the problem. “Something has to be done about this. It will get worse as we move to exascale,” Fiala said, referring to how supercomputers of the next decade are expected to have 10 times the computational power that today’s models do.

Today’s techniques for dealing with system failure may not scale very well, Fiala said. He cited checkpointing, in which a running program is temporarily halted and its state is saved to disk. Should the program then crash, the system is able to restart the job from the last checkpoint.

The problem with checkpointing, according to Fiala, is that as the number of nodes grows, the amount of system overhead needed to do checkpointing grows as well — and grows at an exponential rate. On a 100,000-node supercomputer, for example, only about 35 percent of the activity will be involved in conducting work. The rest will be taken up by checkpointing and — should a system fail — recovery operations, Fiala estimated.

Because of all the additional hardware needed for exascale systems, which could be built from a million or more components, system reliability will have to be improved by 100 times in order to keep to the same MTBF that today’s supercomputers enjoy, Fiala said.

Fiala presented technology that he and fellow researchers developed that may help improve reliability. The technology addresses the problem of silent data corruption, when systems make undetected errors writing data to disk.

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